1. Field of the Invention
The present invention relates to a delay time verifying system and a delay time verifying method, for verifying a delay time of a delay time verification section.
2. Description of the Related Art
In the design of a semiconductor device, timing verification (delay time verification) is carried out to verify whether a designed circuit is operable at designed timings. Such timing verification is carried out in the following manner. Here, it is supposed that a semiconductor device to be designed contains in a circuit section shown in FIG. 6. In this case, the circuit section from the output of a flip-flop A (31) to an input of a flip-flop B (32) is verified as a delay time verification section. In the timing verification, a delay time of the delay time verification section is calculated, and then whether predetermined timing constraint is met is verified based on the calculated delay time. Specifically, whether a setup time and hold time of the flip-flop B (32) are met is verified based on the delay time. When the delay time does not meet the timing constraint, there is a fear that the circuit does not operate correctly because the operation of the flip-flop B (32) is not stabilized.
In the cell-base designing, usually, a delay time table is preserved in a delay time library for each cell to indicate a two-dimensional relation of a load capacitance of the cell and a waveform slew (input slew). Here, the input slew is provided as a time necessary for a signal voltage to rise from 0 volt to a power supply voltage VDD, or a time necessary for the signal voltage to drop from the power supply voltage VDD to 0 V. An example of the delay time table is shown in the following Table 1.
TABLE 1Trf1Trf2Trf3Trf4. . .Cload1Tpd11Tpd12Tpd13Tpd14. . .Cload2Tpd21Tpd22Tpd23Tpd24. . .Cload3Tpd31Tpd32Tpd33Tpd34. . .Cload3Tpd41Tpd42Tpd43Tpd44. . ...................In the table, “Cload” represents a load capacitance, “Trf” represents an input slew, and “Tpd” represents a delay time determined based on a combination of the load capacitance and the input slew. Specifically, the load capacitance of a cell is “Cload1”, the input slew thereof is Trf3, and the delay time table is referred to to determine the delay time of the cell to be Trf13 When the load capacitance and input slew of a cell is not written in the table, the delay time of the cell can is calculated through interpolation.
The delay time from the flip-flop A (31) to the flip-flop B (32) is determined as a summation of delay times of logical circuits A (33) to D (36) existing in the delay time verification section. The load capacitance and input slew of a cell corresponding to each of the logical circuits A (33) to D (36) are previously estimated. The delay time of each cell is determined by referring to the delay time table for every cell stored in a delay time library (not shown) based on the estimated load capacitances and input slews. Such a conventional technique is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 10-116300).
The cell is usually formed from transistors. A switching speed of each transistor is variable depending on a process condition, variations in power supply voltage, or a peripheral temperature (ambient temperature). Specifically, the switching speed of the transistor is faster when the process condition is good, the power supply voltage is higher, or the ambient temperature is lower. The delay time of the cell varies as the result of the variation in the switching speed of the transistor. Therefore, the delay time of the delay time verification section satisfies a predetermined timing constraint under a certain condition, but does not satisfy the timing constraint under another condition. In order to guarantee a correct operation of the semiconductor device to be designed within an operation guarantee range, it should be verified that the delay time verification section satisfies the predetermined timing constraints in the overall range of the variations even when the delay times of the respective cells are varied.
In the conventional technique, it is obvious that the switching speed is faster when the temperature is lower, and is slower when the temperature is higher. For this reason, whether the delay time satisfies the predetermined timing constraint is verified when the delay time of the delay time verification section is shortest. At this time, the delay time is calculated by using a delay time table (delay time MIN table) which is produced under the condition that the process conditions are good, the power supply voltage is maximum within the operation guarantee voltage range, and the ambient temperature is minimum within the operation guarantee temperature range. On the other hand, whether the delay time satisfies the predetermined timing constraint is verified when the delay time of the delay time verification section is longest. The delay time is calculated by using a delay time table (delay time MAX table) which is produced under the conditions that the process conditions are bad, the power supply voltage is minimum within the operation guarantee voltage range, and the ambient temperature is maximum within the operation guarantee temperature range.
FIG. 7 is a diagram showing a time change of an output voltage of a transistor in transition from LOW to HIGH at a high temperature and a low temperature. Generally, in the transistor, the number of carriers at the low temperature is less than the number of carriers at the high temperature. Accordingly, the threshold voltage of the transistor at the low temperature is higher than the threshold voltage thereof at the high temperature. FIG. 7 shows the time necessary for the transistor to reach an ON state when a signal for turning on a transistor is supplied at a same timing in the high temperature and the low temperature. As shown in FIG. 7, the output voltage in the high temperature is higher than that in the low temperature in an initial stage of switching.
On the other hand, the carrier mobility in the low temperature is larger than in the high temperature. Accordingly, an ON current in the low temperature is higher than that in high temperature. A rising speed of the output voltage (voltage variation amount/time) is proportional to the ON current. Accordingly, the rising speed of the output voltage is higher in the low temperature than in the high temperature after the transistor has become the ON state. For this reason, generally, as shown in FIG. 7, the output voltage in the low temperature exceeds the output voltage in the high temperature at a certain time point, and rises earlier to the power supply voltage than in the high temperature. In the above, a case has been described that the output of the transistor changes from LOW to HIGH. A case is similar that the transistor changes from HIGH to LOW.
As described above, generally, while the output voltage of the cell (circuit) begins to change earlier in the high temperature, the output voltage in the low temperature shortly exceeds the output voltage in the high temperature. For this reason, it could be considered that the effect of the phenomenon that the output voltage in the high temperature changes earlier at the initial stage of switching is insignificant if the power supply voltage is sufficiently high compared with the threshold voltage. However, in recent nanometer-generation transistors, the power supply voltage is lower compared with that of a conventional generation transistor, and the difference between the threshold voltage and the power supply voltage is small. Whether the switching of a cell is completed is generally determined based on whether the output voltage of the cell has passed a predetermined voltage, e.g., a half (½) value of the power supply voltage. Therefore, when the difference between the threshold voltage and the power supply voltage is small, there is a possibility that it is determined in the high temperature that the circuit has switched at the initial stage of switching. That is, the switching speed is increased as the temperature is increased, so that inverse phenomenon is caused in temperature characteristic of the switching speed. This is disclosed in “Temperature Effect on Delay for Low Voltage Applications (CMOS jCs)” by Daga, J. M; Ottaviano, E; and Auvergne, D, (Design, Automation and Test in Europe, 1998, Proceedings, 1998).
The inverse phenomenon in the temperature characteristics is dependant upon parameters such as load capacitance, input slew, and circuit configuration, but is not always caused in transistors of a specific generation. Therefore, a case would occur that the inverse phenomenon in the temperature characteristics is caused in one of the cells in a delay time verification section, but is not caused in another cell. When the delay time verification section contains a cell that the inverse phenomenon is caused in the temperature characteristic, a delay time exists which is shorter than the delay time determined by referring to the delay time MIN table produced under the condition at the lowest temperature in the operation guarantee range. Also, a delay time exists which is longer than the delay time determined by referring to the delay time MAX table produced under the condition at the highest temperature in the operation guarantee range. Consequently, in the conventional timing verification method, whether the delay time satisfies the predetermined timing constraint cannot be determined over the entire operation guarantee range.